Into Computers

Ola Dahl

July 29, 2019

Welcome

This is a book about computers. It describes how a small computer can be designed and implemented, using a step-by-step approach.

Starting with a simple building block that can store one bit, we continue, via registers and control logic and instruction decoding, towards a design that can run a small program.

We extend the instruction set, by adding instructions for controlling the program flow, and for interacting with the outside world, through a UART.

We stop when we have a computer that can run a program that has been compiled and linked using gcc.

We implement a subset of a real computer architecture - the RISC-V architecture. In this way, we can convey the experience of building a real system, while at the same time making the task small enough to be completed without a large implementation effort.

Using an already available architecture also allows us to use available tools, such as this RISC-V toolchain.

The book is designed as a Layered Book. This means that there are common parts, covering the general aspects of computer design, but also specific parts, treating layer-specific material. Each layer represents a particular design language, such as VHDL or Verilog.

You can read the book one layer at the time, but you can also move from one layer to another.

The book has the following layers.

You are now reading the VHDL layer. The purpose of this layer is to show how VHDL can be used to construct a computer that implements a specific architecture.

Moving between layers is done by following links. Here is an example.

This is the VHDL layer The other layers are: Verilog SystemC/TLM

You will see these links throughout the book, e.g. at the beginning or the end of a section. Following such a link will take you to another layer. You will arrive a the new layer at a position corresponding to the position from which you left off.

Acknowledgements

This book has been produced using pandoc and Python.

The html-version of the book has been styled using a slightly modified version of this css file from this pandoc demo page.

Choosing a Language

This is the VHDL layer The other layers are: Verilog SystemC/TLM

We describe our computer using a design language. In this way, we can have a textual representation of the computer, and we can use the textual representation as input to software tools, that will help us to simulate the behavior of our computer.

VHDL is a hardware description language. We use VHDL to describe our computer, and to simulate its functionality. It is also possible to use VHDL to actually synthesize a computer, in real hardware, for example in an FPGA.

VHDL is standardized by IEEE.

Information about VHDL can be found e.g. from Doulos.

Hello World

This is the VHDL layer The other layers are: Verilog SystemC/TLM

A simple example will get us started. We use a classical “Hello, world’’ example, which will do nothing meaningful except printing a text string. The code for the example is shown in Figure 1.

The code for the example is from the GHDL guide. We will start using GHDL in Section Getting some tools.

use std.textio.all;

entity hello_world is
end hello_world;

architecture behavior of hello_world is
begin
  process
    variable the_line: line;
  begin
    write(the_line, String'("Hello, world"));
    writeline(output, the_line);
    wait;
  end process;
end behavior;

hello.vhdl

Figure 1. A hello world example in VHDL.

The code in Figure 1 starts with a use clause. The purpose of this clause is to indicate which VHDL libraries that will be used. In this case we use one library, with functionality for printing text.

The code in Figure 1 contains an entity. The entity is empty, since we do not have any input ports or output ports.

Then comes the architecture part, where a process is defined.

The process assigns a string to a variable called the_line. The string is then printed, and a call to wait is done, for the purpose of pausing the simulation.

We remark that the code in Figure 1 generates an artificial, simulated behavior. It does not provide any code that can be used for synthesizing actual hardware.

You can read about VHDL in Wikipedia, and at other places. A book called Free Range VHDL is available for free download. You may also want to look at this VHDL Guide from Doulos.

Getting some Tools

This is the VHDL layer The other layers are: Verilog SystemC/TLM

We need some tools, in the form of software. We search for software that can be obtained without cost.

We use a Linux computer with Ubuntu 18.04, and a Mac computer with macOS Mojave.

We decide to use GHDL.

We can install GHDL in Ubuntu, by building GHDL from source. This requires downloading of source code, and a sequence of build commands. Some notes from such an installation are given in this blog post about Installing GHDL in Ubuntu 16.04.

We can install GHDL on Mac, by downloading from this GHDL Download page.

We download the ghdl mcode version for Mac OS X, which results in download of a file named ghdl-0.36-macosx-mcode.tgz.

In a terminal, we navigate to a directory where we have stored the downloaded file, where we do

tar zxvf ghdl-0.36-macosx-mcode.tgz

We create a directory where we want to store ghdl, and we move the unpacked files to that directory, as

sudo mkdir /usr/local/ghdl_mcode
sudo mv bin /usr/local/ghdl_mcode/
sudo mv lib /usr/local/ghdl_mcode/
sudo mv include /usr/local/ghdl_mcode/

Make it Run

This is the VHDL layer The other layers are: Verilog SystemC/TLM

The code in Figure 1 can be compiled and run.

We start by adding ghdl, which has been installed as described in Section Getting some tools, to the search path for commands. We do this by issuing the command

export PATH=/usr/local/ghdl_mcode/bin/:$PATH

Assuming that the program is stored in a file hello.vhdl, compiling can be done as

ghdl -a hello.vhdl

The above command generates the file hello.o, which can be elaborated, using the command

ghdl -e hello_world

where the string hello_world refers to the name of the entity in Figure 1.

The code can now be run, by doing

ghdl -r hello_world

which results in the printout

Hello, world

Building a Computer

This is the VHDL layer The other layers are: Verilog SystemC/TLM

We have chosen a language, to describe our computer. We have taken a first, tiny step, and we have seen how we can get hold of some tools.

Our goal is to create a computer that can run programs, consisting of instructions. We want the instructions to be generated, using a compiler.

A computer reads instructions from a memory. Each instruction is represented as a sequence of bits. The values of the bits determine the type of instruction, and sometimes also arguments that the instruction shall use. The allowed instructions, for a given computer, belong to the computer’s instruction set.

Most computers have instructions for loading data from a memory, and storing data to a memory. Other common instructions are instructions for doing mathematical operations, such as addition and subtraction, and instructions for making decisions. The decisions can be based on evaluations of certain conditions, such as checking if a number is zero, or if a certain bit is set in a piece of data.

An instruction that has been read from memory is decoded, meaning that the computer interprets the bits of the instruction, and then, depending on the values of the bits, takes different actions.

The actions taken are determined by the instructions. As an example, an instruction for addition results in the actual addition of two numbers, and most often also the storing of the result of the addition.

Storing one Bit

We start with a small building block, that can store only one bit. We then extend the building block, so that we can store larger pieces of information. At a certain stage in our development, we are ready to implement our first instruction.

A bit can have the values 0 or 1. In a computer, these values are represented by a low value and a high value of an electrical signal.

The value of a bit can be stored. This means that the value is remembered, as long as it is stored. While the value is stored, the value can be read, and used, for the purpose of performing different operations. As an example, a bit could be used in an addition operation, or it could be copied so that it is stored somewhere else, for example at another place in a memory.

A D Flip-flop

This is the VHDL layer The other layers are: Verilog SystemC/TLM

The value of a bit can be stored in a building block called D flip-flop.

A D flip-flop stores one bit of data. A new value can be stored when a clock signal changes value. A component, which can change its stored value only when a clock signal changes, is called a synchronous component.

A D flip-flop implementation in VHDL is shown in Figure 2.

library ieee;
use ieee.std_logic_1164.all; 

entity d_ff is
  port(
    clk: in std_logic;
    data_in: in std_logic;
    data_out: out std_logic);
  end d_ff;

architecture rtl of d_ff is

  signal reg_value: std_logic;

begin

  update: process(clk)
  begin
    if rising_edge(clk) then
      reg_value <= data_in;
    end if;
  end process; 

  data_out <= reg_value;

end rtl; 

d_ff.vhdl

Figure 2. A D flip-flop in VHDL.

The code in Figure 2 starts with a reference to a library. We use the library to get access to a data type called std_logic. Variables of this data type represent binary data.

An entity is then defined. The entity has a port where inputs and outputs are defined. We have two inputs, called clk and data_in, and we have one output, called data_out.

The architecture block, which is called rtl, for register-transfer level, defines a variable called reg_value. The variable reg_value is defined using the keyword signal.

The variable reg_value will contain the actual value stored in the D flip-flop.

The variable reg_value is called a state variable.

A VHDL process called update defines actions to be taken at every rising edge of the clock signal. We see that the only action taken is to assign the value of the input data_in to the state variable reg_value. This assignment ensures that the state variable reg_value is updated at every rising edge of the clock.

An assignment of the variable data_out is done, outside of the process update. This assignment ensures that the output data_out has the same value as the current value of the state variable reg_value.

A Testbench

This is the VHDL layer The other layers are: Verilog SystemC/TLM

The D flip-flop implementation in Figure 2 has inputs and outputs. An external module, referred to as a testbench, can be used for the purpose of generating input signals to the D flip-flop, and observing output signals from the D-flip-flop.

A VHDL testbench is shown in Figure 3.

library ieee; 
use ieee.std_logic_1164.all;

entity d_ff_tb is
end d_ff_tb;

architecture behavior of d_ff_tb is

  component d_ff
    port(
      clk: in std_logic;
      data_in: in std_logic;
      data_out: out std_logic);
  end component;

  signal clk: std_logic := '1';

  constant clk_half_period: time := 2 ns; 
  constant n_clk_cycles: integer := 4; 

  signal d_ff_data_in: std_logic := '1'; 
  signal d_ff_data_out: std_logic;

begin

  d_ff_0: d_ff
    port map(
      clk => clk,
      data_in => d_ff_data_in,
      data_out => d_ff_data_out);

  clk_gen: process is
  begin
    for i in 1 to n_clk_cycles loop
      clk <= '1';
      wait for clk_half_period;
      clk <= '0';
      wait for clk_half_period; 
    end loop;
    wait; 
  end process;

  stim_gen: process is
  begin
    wait for 1 ns;
    d_ff_data_in <= '0';
    wait for 5 ns;
    d_ff_data_in <= '1';
    wait for 3 ns;
    d_ff_data_in <= '0';
    wait;
  end process; 

  reporter: process(clk, d_ff_data_in) is
  begin
    if (rising_edge(clk) or d_ff_data_in'event) then
       report "data_in=" & std_logic'image(d_ff_data_in) & 
              ", data_out=" & std_logic'image(d_ff_data_out);
    end if; 
  end process; 

end behavior; 

d_ff_tb.vhdl

Figure 3. A D flip-flop testbench in VHDL.

The testbench in Figure 3 starts with a library reference, followed by a definition of an empty entity. The architecture section defines a signal variable called clk. This variable represents the clock signal. The actual shape of the clock signal is defined in the process named clk_gen, by the lines

      clk <= '1';
      wait for clk_half_period;
      clk <= '0';
      wait for clk_half_period; 

The input signal to the D flip-flop is defined by the signal variable d_ff_data_in. The values used for the input signal are defined in the stim_gen process, as

  stim_gen: process is
  begin
    wait for 1 ns;
    d_ff_data_in <= '0';
    wait for 5 ns;
    d_ff_data_in <= '1';
    wait for 3 ns;
    d_ff_data_in <= '0';
    wait;
  end process; 

The architecture section of the testbench in Figure 3 is named behavior, to indicate that the testbench is a behavioral model. A behavioral model can be used in simulation, but can not be synthesized into a working digital system, for use in e.g. an FPGA or an ASIC.

Build and Run

This is the VHDL layer The other layers are: Verilog SystemC/TLM

The D flip-flop in Figure 2 and the testbench in Figure 3 can be analyzed using

ghdl -a d_ff.vhdl 
ghdl -a d_ff_tb.vhdl 

The combined system, containing the D flip-flop and the testbench, can be elaborated by the command

ghdl -e d_ff_tb

The simulation can be run by giving the command

ghdl -r d_ff_tb

The resulting printout is shown in Figure 4.

d_ff_tb.vhdl:63:8:@1ns:(report note): data_in='0', data_out='U'
d_ff_tb.vhdl:63:8:@4ns:(report note): data_in='0', data_out='U'
d_ff_tb.vhdl:63:8:@6ns:(report note): data_in='1', data_out='0'
d_ff_tb.vhdl:63:8:@8ns:(report note): data_in='1', data_out='0'
d_ff_tb.vhdl:63:8:@9ns:(report note): data_in='0', data_out='1'
d_ff_tb.vhdl:63:8:@12ns:(report note): data_in='0', data_out='1'

Figure 4. Printout from running the testbench in Figure 3.

The printout in Figure 4 shows the values of data_in and data_out for a sequence of time instants. The VHDL code that does the printout is located inside an if-statement in the reporter process in Figure 3, and shown here as

  reporter: process(clk, d_ff_data_in) is
  begin
    if (rising_edge(clk) or d_ff_data_in'event) then
       report "data_in=" & std_logic'image(d_ff_data_in) & 
              ", data_out=" & std_logic'image(d_ff_data_out);
    end if; 
  end process; 

The effect is that a printout is done whenever the clock signal has a rising edge, or the variable d_ff_data_in changes value. The changes for the variable d_ff_data_in are defined in the stim_gen process in Figure 3.

Making Waves

This is the VHDL layer The other layers are: Verilog SystemC/TLM

The testbench in Figure 3 generates printouts as shown in Figure 4. The printouts show values of digital signals, each having the value one or zero. We can represent these signals as waveforms, with the level of the waveform being one or zero. Thinking of the value one as a high voltage level, and the value zero as a low voltage level, we can think of the waveforms as representing actual voltages, in an actual digital system.

A waveform can be visualized using the GTKWave program. We can download a GTKWave version for Mac, in the form of a zip-file that contains an app folder with an executable GTKWave program. The GTKWave program can be started from a Mac Terminal (after first having started it via the GUI via right-clicking on the app folder of the program and selecting Open - since I was sure that I wanted to open it) by giving the command open followed by the app file name of the program. As an example, I could start the program by doing

open /Users/ola/prog/gtkwave/gtkwave.app

A GTKWave version for Ubuntu can be installed in Ubuntu, by giving the command

sudo apt-get install gtkwave

The program can then be started by giving the command gtkwave.

A waveform can be generated from VHDL by running the ghdl program with an added command line switch. As a first step, we use ghdl commands as described in Section Build and Run for analysis and elaboration. The command line switch –vcd is then added to the ghdl command for running the simulation, as

ghdl -r d_ff_tb --vcd=d_ff_tb_wave.vcd

Waveforms, generated from the testbench in Figure 3, are shown in Figure 5.

fig_d_ff_tb_wave

Figure 5. Waveforms, obtained from running the testbench in Figure 3.

We see in Figure 5 how the waveforms correspond to the printouts shown in Figure 4.

Storing Data in Registers

When a computer executes instructions, it often needs intermediate storage places. As an example, consider an addition of two data items, both stored in memory. In this situation, it might be convenient to read the data items from memory and store them in an intermediate storage place, from where the inputs to the addition operation can be taken. The result of the addition could also be stored in the intermediate storage area, before it is transferred to memory.

An intermediate storage place can consist of a register, or a set of registers. A register typically allows faster accesses, for reading and writing data, than a memory.

A set of registers could be used when performing an addition. Two items of data could be read from memory, and stored in two registers. A third register, or one of the two already used, could be used to store the result of the addition, before it is written back to memory.

Registers can also be used to hold other types of values. As an example, a register is often used for holding the current value of the program counter

We could also use registers for holding status bits, that provide information about the result of a computation. One example of such a register is a status register. A status register can hold information indicating, for example, if an addition resulted in overflow, or if an operation resulted in a zero value.

A set of registers, organized together, so that it is possible to refer to each of the individual registers, for example using an address, can be called a register file.

A Register

A D flip-flop can store one bit. We can imagine a register as a row of D flip-flops, each storing one bit, with the possibility to load new values into all D flip-flops simultaneously.

This is the VHDL layer The other layers are: Verilog SystemC/TLM

A register implementation in VHDL is shown in Figure 6.

library ieee;
use ieee.std_logic_1164.all; 

entity n_bit_register is
  generic (N: integer := 8); 
  port(
    clk: in std_logic;
    data_in: in std_logic_vector(N-1 downto 0);
    data_out: out std_logic_vector(N-1 downto 0));
  end n_bit_register;

architecture rtl of n_bit_register is

  signal reg_value: std_logic_vector(N-1 downto 0);

begin

  update: process(clk)
  begin
    if rising_edge(clk) then
      reg_value <= data_in;
    end if;
  end process; 

  data_out <= reg_value;

end rtl; 

n_bit_register.vhdl

Figure 6. A register in VHDL.

The code in Figure 6 defines an entity called n_bit_register. The entity has a port where inputs and outputs are defined. We have two inputs, called clk and data_in, and we have one output, called data_out.

The architecture block defines a variable called reg_value. The variable reg_value will contain the actual value stored in the register.

A VHDL process called update ensures that the state variable reg_value is updated at every rising edge of the clock.

An assignment of the variable data_out is done, outside of the process update. This assignment ensures that the output data_out has the same value as the current value of the state variable reg_value.

A Testbench

An external module, referred to as a testbench, can be used for the purpose of generating input signals to, and observing output signals from, the register in Figure 6.

In the testbench module, we use a parameter, to specify the width of the register.

This is the VHDL layer The other layers are: Verilog SystemC/TLM

The parameter is defined as a VHDL constant, as

  constant N: integer := 4;

The clock signal is generated using a variable named clk, together with two constants, as

  signal clk: std_logic := '0';

  constant clk_half_period: time := 2 ns; 
  constant n_clk_cycles: integer := 5; 

The actual clock generation is done in a VHDL process, as

  clk_gen: process is
  begin
    for i in 1 to n_clk_cycles loop
      clk <= '1';
      wait for clk_half_period;
      clk <= '0';
      wait for clk_half_period; 
    end loop;
    wait; 
  end process;

The generation of input signals to the register in Figure 6 is done using a VHDL process, as

  stim_gen: process(clk) is
  begin
    if (rising_edge(clk)) then
      reg_data_in <= std_logic_vector(
        unsigned(reg_data_in) + 1);
    end if; 
  end process; 

The input signal and the output signal are defined as

  signal reg_data_in: std_logic_vector(N-1 downto 0) :=
    (0 => '1', others => '0'); 
  signal reg_data_out: std_logic_vector(N-1 downto 0);

The signals are used in the instantiation of the register, which is done as

  n_bit_register_0: n_bit_register
    port map(
      clk => clk,
      data_in => reg_data_in,
      data_out => reg_data_out);

The reporting of the results is done in a process, as

  reporter: process(clk) is
  begin
    if (rising_edge(clk)) then
       report "data_in=" &
         reverse_string(std_logic_vector_to_string(reg_data_in)) & 
         ", data_out=" &
         reverse_string(std_logic_vector_to_string(reg_data_out));
    end if; 
  end process; 

Build and Run

The register in Figure 6 and a testbench, with code as shown in in Section A Testbench, can be built and run.

A makefile can be created. The makefile can contain commands for building and running the register and the testbench.

This is the VHDL layer The other layers are: Verilog SystemC/TLM

A makefile is shown in Figure 7.


SOURCES := n_bit_register.vhdl n_bit_register_tb.vhdl

n_bit_register_tb: $(SOURCES)
    ghdl -a $^
    ghdl -e $@

.PHONY: clean

clean: 
    rm work-obj93.cf

Makefile

Figure 7. A makefile for building and running the register in Figure 6.

It can be seen, in the makefile in Figure 7, that the ghdl command is used, in the same way as described in Section Build and Run in Chapter Storing one bit.

Assume the register is stored in a file named n_bit_register.vhdl, and the testbench is stored in a file named n_bit_register_tb.vhdl. Running the makefile, by giving the command make results in printouts, as

$ make
ghdl -a n_bit_register.vhdl n_bit_register_tb.vhdl
ghdl -e n_bit_register_tb

A script file can be created, and used for running the simulated register and the testbench. Using a script file named run.sh, with contents as

#!/bin/bash

ghdl -r n_bit_register_tb --vcd=n_bit_register_tb_wave_vhdl.vcd

for running the simulation, gives the result as shown in Figure 8.

$ ./run.sh 
n_bit_register_tb.vhdl:110:8:@0ms:(report note): data_in=0001, data_out=UUUU
n_bit_register_tb.vhdl:110:8:@4ns:(report note): data_in=0010, data_out=0001
n_bit_register_tb.vhdl:110:8:@8ns:(report note): data_in=0011, data_out=0010
n_bit_register_tb.vhdl:110:8:@12ns:(report note): data_in=0100, data_out=0011
n_bit_register_tb.vhdl:110:8:@16ns:(report note): data_in=0101, data_out=0100

Figure 8. Printouts from a simulation of the register in Figure 6.

We can generate waveforms, in the same way as described in Section Making Waves. The resulting waveform, for the register with printouts as shown above, is displayed in Figure 9.

fig_n_bit_register_tb_wave_vhdl

Figure 9. Waveforms from a simulation with printouts as shown in Figure 8.

Our First Instruction

A computer executes programs by following instructions. The instructions belong to an instruction set. As mentioned in Chapter Welcome, we will use a subset of the RISC-V architecture as the instruction set for our computer.

As a first step, we will try to build a computer with only one instruction. Although somewhat restricted, this computer will be able to

We will start with deciding on a program to run on our computer. The program will be stored in a memory, and its instructions will be read, one by one, and actions will be taken.

A Program

From the RISC-V architecture page, we can download the the RISC-V Instruction Set Manual ISA.

We look for an instruction that can load a value into a register. Using such an instruction, we can create a small program that loads specified values into some of the registers.

We choose to used the RV32I Base Integer Instruction Set, which is described in Chapter 2 of ISA.

The instructions in this instruction set set are 32 bits.

The bits in an instruction are numbered, with 31 for the leftmost bit, down to 0 for the rightmost bit.

We use the notation b1:b2 to describe a range of bits, such as 31:0 for describing all 32 bits, or e.g. 7:0 for describing the rightmost byte.

In Section 2.3 of ISA we can see how 32-bit instructions that handle immediate data are encoded.

One instruction format is called U-type. The bits in U-type instructions are described as

In Section 2.4 of ISA, we find a description of the instruction LUI, which stands for load upper immediate, and which is used to “build 32-bit constants”.

We also see that the LUI instruction “places the U-immediate value in the top 20 bits of the destination register rd, filling in the lowest 12 bits with zeros”.

We conclude that

In Chapter 25 in ISA, in Table 25.1, we see that the opcode for LUI is 0110111.

We can write the LUI instruction, with the fields as described above, as a 32-bit binary word. The resulting format is illustrated in Figure 10, as

imm (31:12), rd (11:7), LUI opcode(0110111)

Figure 10. Instruction format for the LUI instruction, adapted from Table 25.1 in ISA.

In order to create a program that stores values into registes, we should select which registers to use.

In Section 2.1 in ISA, we see that there are 32 registers, each 32-bits wide, referred to as registers x0 to x31.

We also see that in register x0, all bits are hardwired to the value zero.

For the other registers, we see, in Chapter 26 in ISA, in Table 26.1, that the registers have different roles. In these rolese, the registers have alternative names, indicating their roles.

For example, register x1 (named ra) is used as return address and register x2 (named sp) is used as stack pointer.

There are also registers that are used for storage of temporary values, such as x5 (named t0, and also serving as alternate link registers), and x6 and x7 (named t1 and t2, respectively).

Using the alternative names, which are referred to ABI names in Table 26.1 in ISA, and which also can be referred to as assembler mnemonics due to their usage in assembly programs (ref URL), we can create a program that performs actions, as

  1. write three different values to registers t0, t1, and t2.
  2. write the value zero to registers t0, t1, and t2

In assembly language, we could write a program, using lowercase for the instruction name, as

lui t0, 1
lui t1, 2
lui t2, 3
lui t0, 0
lui t1, 0
lui t2, 0

Figure 11. An assembly program, using a LUI instruction to write values to registers.

Here we should note, again, that the LUI instruction writes the immediate value, which is 1 for the first instruction in our program, to the top 20 bits of the destination register, which for this instruction is t0, while at the same time filling in the lowest 12 bits with zeros.

For the first instruction in Figure 10, which is

lui t0, 1

this means that the number being stored in t0 is 1 followed by 12 zeros. In binary form, this becomes

1000000000000

Counting the bits from right to left, with the rightmost bit having number zero, we know, from the properties of binary numbers (ref) that the n^th bit has the weight 2^n.

In this number, all weights are zero except for bit number 12. This gives the corresponding decimal number as

2^12 = 4096

We can write this number also in hexadecimal form. One way of arriving at the hexadecimal representation is to start with the binary representation, in this case

1000000000000

and then group the bits, in groups of four bits in each group. This gives

1 0000 0000 0000

We then let each group of four bits be represented by one hexadecimal digit. Using the prefix 0x, which is commonly used for to indicate that a number is hexadecimal, we get

1 0000 0000 0000 = 0x1000

In a similar way, we can calculate the value that will be stored in register t1, by the instruction

lui t1, 2

as

10 0000 0000 0000 = 0x2000

which, when converted to decimal form, becomes

0x2000 = 8192

For the third instruction in Figure 10,

lui t2, 3

the corresponding calculation yields

0x3000 = 12288

In order to run the program in Figure 11 on our computer, which will be build in the sections that follow, we need to write the program using binary code.

We saw , in Chapter 25 in ISA, in Table 25.1, that the opcode for LUI is 0110111, and we have seen how the top 20 bits of the value to be stored in the destination register are represented in the instruction.

We see, in Chapter 26 in ISA, in Table 26.1, how registers t0, t1, and t2 are ABI names for the registers x5, x6, and x7.

Using the numeric values 5, 6, and 7 for these registers, we can now write the program in Figure 11 in binary code, as

00000000000000000001 00101 0110111
00000000000000000010 00110 0110111
00000000000000000011 00111 0110111
00000000000000000000 00101 0110111
00000000000000000000 00110 0110111
00000000000000000000 00111 0110111

Grouping the binary digits in groups of four gives

0000 0000 0000 0000 0001 0010 1011 0111
0000 0000 0000 0000 0010 0011 0011 0111
0000 0000 0000 0000 0011 0011 1011 0111
0000 0000 0000 0000 0000 0010 1011 0111
0000 0000 0000 0000 0000 0011 0011 0111
0000 0000 0000 0000 0000 0011 1011 0111

We can convert the program to a representation where we use hexadecimal numbers. This conversion results in the program shown in Figure 12.

0x000012B7
0x00002337
0x000033B7
0x000002B7
0x00000337
0x000003B7

Figure 12. A binary program, using a LUI instruction to write values to registers.

Addressing a Memory

FROM HERE ON THE BOOK IS IN A MORE WORK-IN-PROGRESS STATE

WORK IS ONGOING TO COMPLETE THE BOOK, AND RELEASE IT

We can store a program, like the program shown in Figure 12, in a memory.

The program in Figure 12 consists of instructions. Each instruction is represented by a 32-bit word.

As a first step towards executing the program, we can create a program counter that reads the 32-bit instructions, one by one, from a memory.

Reading an instruction is done by using the program counter value to address the memory. When we are done with reading an instruction, we might want to read the next instruction.

We could imagine a program counter that refers to a specific 32-bit word, stored in the memory. In a program with 32-bit instructions, like the program in Figure 12, this makes it possible to read the next instruction by adding one to the program counter.

Another alternative is to let the program counter represent an address expressed in bytes. In such a situation, we can read the next instruction by incrementing the program counter by four. This type of addressing is referred to as byte-addressing.

This is the VHDL layer The other layers are: Verilog SystemC/TLM

A memory implementation in VHDL is shown in Figure 13.

library ieee;
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;

library std;
use std.textio.all;

library work;
use work.string_lib.all;

entity memory is
  generic (address_width: integer := 32;
           data_width: integer := 32;
           size: integer := 256);
  port(
    clk: in std_logic;
    write_enable: in std_logic; 
    address: in std_logic_vector(address_width-1 downto 0); 
    data_in: in std_logic_vector(data_width-1 downto 0);
    data_out: out std_logic_vector(data_width-1 downto 0));

end memory;

architecture rtl of memory is

  type memory_type is array(0 to size-1) of
    std_logic_vector(data_width-1  downto 0); 

  impure function init_memory return memory_type is
    file in_file: text is in "memory_contents.txt";
    variable in_line: line;
    variable s: std_logic_vector(data_width-1 downto 0);
    variable memory: memory_type; 
  begin
    report "length of memory is " & integer'image(memory'length); 
    for i in 1 to integer(memory'length) loop
      if not endfile(in_file) then
        readline(in_file, in_line);
        hread(in_line, s);
        memory(i-1) := s; 
      else
        memory(i-1) := (others => 'X');
      end if; 
    end loop;
    return memory;
  end function;
  
  signal memory: memory_type := init_memory;

begin

  update: process(clk)
  begin
    if rising_edge(clk) then 
      if write_enable = '1' then
        memory(to_integer(unsigned(address))) <= data_in;
      end if;
    end if;
  end process;
  
  data_out <= memory(to_integer(unsigned(address))); 

end rtl; 

memory.vhdl

Figure 13. A memory in VHDL.

The memory implementation in Figure 13 uses an array to represent the actual storage.

A program counter implementation in VHDL is shown in Figure 14.

library ieee;
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all;

entity pc is
  generic (pc_width: integer := 32); 
  port(
    clk: in std_logic;
    pc_out: out std_logic_vector(pc_width-1 downto 0) := (others => '0'));
  end pc;

architecture rtl of pc is

  signal pc_value: std_logic_vector(pc_width-1 downto 0) := (others => '0');

begin

  update: process(clk)
  begin
    if rising_edge(clk) then
      pc_value <= std_logic_vector(unsigned(pc_value) + 4);
    end if;
  end process; 

  pc_out <= pc_value;

end rtl; 

pc.vhdl

Figure 14. A program counter in VHDL.

Connect the pc and the memory into a design, so that when it runs, the program is read, and printed.

We define signals, such as pc

  signal pc_value: std_logic_vector(address_width-1 downto 0);

and data read from the memory

  signal data_out: std_logic_vector(data_width-1 downto 0);

and clock signal, as

  signal clk: std_logic := '0';

  constant clk_half_period: time := 2 ns; 
  constant n_clk_cycles: integer := 7; 

The clock signal is generated as

  clk_gen: process is
  begin
    for i in 1 to n_clk_cycles loop
      clk <= '0';
      wait for clk_half_period;
      clk <= '1';
      wait for clk_half_period; 
    end loop;
    wait; 
  end process;

Decoding the Instruction

Running the program

Hello Assembly World

The Program

l.andi r0, r0, 0
l.addi r0, r0, 0x9
l.slli r0, r0, 28

l.andi r1, r1, 0
l.addi r1, r1, 72
l.sw 0(r0), r1

Tools

Testing in QEMU

or1k-elf-as -o start.o start.s or1k-elf-ld -T default.ld -o prog.elf start.o /home/ola/prog/qemu/bin/qemu-system-or32 -nographic -kernel prog.elf

Extending our Computer

And with Immediate Half Word

We see the instruction format for l.andi rD, rA, K, with its different fields. There are

We can write the instruction, with the fields as described above, as a 32-bit binary word. This gives

101001DDDDDAAAAAKKKKKKKKKKKKKKKK

The binary instruction format for l.andi rD, rA, K can also be seen in Section 17 of the [OpenRISC 100 Architecture Manual][openrisc_arch_manual].

Suppose we want to make a program that uses the andi

In assembly code, this program would be

    l.movhi r0, 0
    l.ori r0, r0, 15
    l.andi r1, r0, 7
    l.andi r2, r1, 3
    l.andi r3, r2, 1

Using the instruction format as described above, we find that the corresponding machine code program becomes

000110 00000 00000 0000000000000000
101010 00000 00000 0000000000001111
101001 00001 00000 0000000000000111
101001 00010 00001 0000000000000011
101001 00011 00010 0000000000000001

Grouping the binary digits in groups of four gives

0001 1000 0000 0000 0000 0000 0000 0000
1010 1000 0000 0000 0000 0000 0000 1111
1010 0100 0010 0000 0000 0000 0000 0111
1010 0100 0100 0001 0000 0000 0000 0011
1010 0100 0110 0010 0000 0000 0000 0001

We can convert the program to a representation where we use hexadecimal numbers. This conversion results in the program shown in Figure 13.

18000000
A800000F
A4200007
A4410003
A4620001

Figure 13. A program using the instruction l.andi.

Store to memory

Running the Program

Hello C World

The Program

Tools

Testing in QEMU

Extending our Computer

Running the Program

References

[ISA], The RISC-V Instruction Set Manual Volume I: Unprivileged ISA, available at this RISC-V architecture page