Welcome

This is a book about computers. It takes a practical approach, illustrating how a small computer can be designed, and implemented, using a step-by-step approach.

Starting with a simple building block that can store one bit, we continue, via registers and control logic and instruction decoding, towards a design that can run a small program.

We extend the instruction set, by adding instructions for controlling the program flow, and for interacting with the outside world (through a UART).

We stop when we have a computer that can run a program that has been compiled and linked using gcc.

We implement a subset of a real computer architecture - the OR1K architecture. In this way, we can convey the experience of building a real system, while at the same time making the task small enough to be completed without a large implementation effort.

Using an already available architecture also allows us to use available tools, such as this gcc with newlib for OR1K.

The book is designed as a Layered Book. This means that there are common parts, covering the general aspects of computer design, but also specific parts, treating layer-specific material. Each layer represents a particular design language, such as VHDL or Verilog.

You can read the book one layer at the time, but you can also move from one layer to another.

The book has the following layers.

You are now reading the SystemC/TLM layer. The purpose of this layer is to show how SystemC and TLM can be used to construct a computer that implements a specific architecture.

Moving between layers is done by following links. Here is an example.

This is the SystemC/TLM layer The other layers are: VHDL Verilog

You will see these links throughout the book, e.g. at the beginning or the end of a section. Following such a link will take you to another layer. You will arrive a the new layer at a position corresponding to the position from which you left off.

Acknowledgements

This book has been produced using pandoc and Python.

The html-version of the book has been styled using a slightly modified version of this css file from this pandoc demo page.

Choosing a Language

This is the SystemC/TLM layer The other layers are: VHDL Verilog

We describe our computer using a design language. In this way, we can have a textual representation of the computer, and we can use the textual representation as input to software tools, that will help us to simulate the behavior of our computer.

SystemC is a C++ library that makes it possible to create event-based simulations. TLM is an additional library that makes it possible to do transaction level simulation. We use SystemC and TLM to describe our computer, and to simulate its functionality.

SystemC and TLM are standardized by IEEE and Accellera.

Accellera provides information about SystemC and TLM.

Hello World

This is the SystemC/TLM layer The other layers are: VHDL Verilog

A simple example will get us started. We use a classical "Hello, world'' example, which will do nothing meaningful except printing a text string. The code for the example is shown in Figure 1.

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#include "systemc"
#include "tlm.h"

#include <iostream>

int sc_main(int argc, char* argv[])
{
    std::cout << "Hello, world" << std::endl; 
    sc_core::sc_start();
    return 0;
}

hello.cpp

Figure 1. A hello world example in SystemC.

The code in Figure 1 starts with three include directives. The first and the second include directive include functionality for SystemC and TLM, respectively. The third include directive includes the iostream header, which contains functionality for printing text.

The code in Figure 1 contains a function named sc_main. The function starts with a statement that prints a string. The simulation is then started, by calling the function sc_core::sc_start, and after that the value zero is returned.

You can read about in SystemC and TLM in Wikipedia, and at other places, such as Doulos, who provides this SystemC Guide.

Getting some Tools

This is the SystemC/TLM layer The other layers are: VHDL Verilog

We need some tools, in the form of software. We search for software that can be obtained without cost.

We use a Linux computer with Ubuntu 16.04, and a Mac computer with OS X El Capitan.

We can download SystemC and TLM from Accellera. We have to accept a license agreement, and then we can download the file systemc-2.3.1a.tar.gz by using the link named Core SystemC Language and Examples.

We unpack the file, using the command

tar zxvf systemc-2.3.1a.tar.gz

Build and install can be done by first creating and visiting a directory objdir as

cd systemc-2.3.1a/
mkdir objdir
cd objdir/

Configure and build can be done as

../configure --prefix=/usr/local/systemc-2.3.1a
sudo mkdir /usr/local/systemc-2.3.1a
make

We can test the build, by doing

make check

which takes some time to execute.

As a last step, we can install by doing

sudo make install

Make it Run

This is the SystemC/TLM layer The other layers are: VHDL Verilog

The program in Figure 1 can be compiled, linked, and run.

Assuming that the program is stored in a file hello.cpp, compiling can be done as

g++ -c -I /usr/local/systemc-2.3.1a/include hello.cpp

The above command generates the object file hello.o, which can be linked into an executable program named hello.

The linking is simplified by setting an environment variable L_SYSTEMC. On Linux, we set the environment variable as

L_SYSTEMC=/usr/local/systemc-2.3.1a/lib-linux64

and on Mac we set it as

L_SYSTEMC=/usr/local/systemc-2.3.1a/lib-macosx64

The linking is now done by the command

g++ -o hello hello.o -L $L_SYSTEMC -lsystemc

The program can be run on Linux by giving the command

LD_LIBRARY_PATH=$L_SYSTEMC ./hello

and on Mac by giving the command

./hello

The resulting printout is of the form

        SystemC 2.3.1-Accellera --- Jan  3 2017 19:23:14
        Copyright (c) 1996-2014 by all Contributors,
        ALL RIGHTS RESERVED
Hello, world

where the date corresponds to the date when you built the SystemC library, as described in Section Getting some tools.

Building a Computer

We have chosen a language, to describe our computer. We have taken a first, tiny step, and we have seen how we can get hold of some tools.

Our goal is to create a computer that can run programs, consisting of instructions. We want the instructions to be generated, using a compiler.

A computer reads instructions from a memory. Each instruction is represented as a sequence of bits. The values of the bits determine the type of instruction, and sometimes also arguments that the instruction shall use. The allowed instructions, for a given computer, belong to the computer's instruction set.

Most computers have instructions for loading data from a memory, and storing data to a memory. Other common instructions are instructions for doing mathematical operations, such as addition and subtraction, and instructions for making decisions. The decisions can be based on evaluations of certain conditions, such as checking if a number is zero, or if a certain bit is set in a piece of data.

An instruction that has been read from memory is decoded, meaning that the computer interprets the bits of the instruction, and then, depending on the values of the bits, takes different actions.

The actions taken are determined by the instructions. As an example, an instruction for addition results in the actual addition of two numbers, and most often also the storing of the result of the addition.

Storing one Bit

We start with a small building block, that can store only one bit. We then extend the building block, so that we can store larger pieces of information. At a certain stage in our development, we are ready to implement our first instruction.

A bit can have the values 0 or 1. In a computer, these values are represented by a low and a high value of an electrical signal.

The value of a bit can be stored. This means that the value is remembered, as long as it is stored. While the value is stored, the value can be read, and used, for the purpose of performing different operations. As an example, a bit could be used in an addition operation, or it could be copied so that it is stored somewhere else, for example at another place in a memory.

A D Flip-flop

This is the SystemC/TLM layer The other layers are: VHDL Verilog

The value of a bit can be stored in a building block called D flip-flop.

A D flip-flop stores one bit of data. A new value can be stored when a clock signal changes value. A component, which can change its stored value only when a clock signal changes, is called a synchronous component.

A D flip-flop implementation in SystemC is shown in Figure 2.

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#include "d_ff.h"

SC_HAS_PROCESS(d_ff);

d_ff::d_ff(sc_core::sc_module_name name):
    sc_module(name) 
{
    SC_METHOD(update);
    sensitive << clk.pos(); 
}

void d_ff::update()
{
    reg_value = data_in.read();
    data_out.write(reg_value);
}

d_ff.cpp

Figure 2. A D flip-flop in SystemC.

The code in Figure 2 starts with an include directive. The include directive refers to a header file called d_ff.h. The header file defines a class called d_ff, as

class d_ff : sc_core::sc_module
{
  public: 
    sc_in<bool> clk;
    sc_in<bool> data_in;
    sc_out<bool> data_out;
    d_ff(sc_core::sc_module_name name); 
  private:
    void update();
    bool reg_value;
}; 

The class defines two inputs, called clk and data_in, and one output, called data_out.

The class also defines a function called update, and a variable called reg_value. The variable reg_value is defined using the keyword bool.

The variable reg_value will contain the actual value stored in the D flip-flop.

The variable reg_value is called a state variable.

The class inherits from another class, called sc_core::sc_module. In this way, the class becomes a SystemC module.

The code in Figure 2 defines the function update to be a SystemC process. This is done using the keyword SC_METHOD. In addition, it defines the module d_ff to be sensitive to rising edges of the clock signal. The result of the sensitivity definition is that the function update will be called at every positive edge of the clock signal.

We see, from the contents of the function update, that the value of the input data_in is assigned to the state variable reg_value. This assignment ensures that the state variable reg_value is updated at every rising edge of the clock.

An assignment of the variable data_out is also done, inside the function update. This assignment ensures that the output data_out has the same value as the current value of the state variable reg_value.

A Testbench

This is the SystemC/TLM layer The other layers are: VHDL Verilog

The D flip-flop implementation in Figure 2 has inputs and outputs. An external module, referred to as a testbench, can be used for the purpose of generating input signals to the D flip-flop, and observing output signals from the D-flip-flop.

A SystemC testbench is shown in Figure 3.

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#include "d_ff_tb.h"

SC_HAS_PROCESS(d_ff_tb);

d_ff_tb::d_ff_tb(sc_core::sc_module_name name):
    sc_module(name),
    d_ff_0("d_ff_0"),
    clk("d_ff_clk", 4, SC_NS, 1.0)
{
    SC_THREAD(stim_gen);
    d_ff_0.clk(clk); 
    d_ff_0.data_in(d_ff_data_in); 
    d_ff_0.data_out(d_ff_data_out);
    SC_METHOD(reporter);
    sensitive << d_ff_0.clk.pos();
    sensitive << d_ff_data_in; 
}

void d_ff_tb::stim_gen()
{
    d_ff_data_in.write(true);
    wait(1, SC_NS);
    d_ff_data_in.write(false);
    wait(5, SC_NS);
    d_ff_data_in.write(true);
    wait(3, SC_NS);
    d_ff_data_in.write(false);
    wait(); 
}

void d_ff_tb::reporter()
{
    std::cout << "Time: " << sc_time_stamp(); 
    std::cout << ", data_in=" << d_ff_data_in.read(); 
    std::cout << ", data_out=" << d_ff_data_out.read()
          << std::endl;
}

d_ff_tb.cpp

Figure 3. A D flip-flop testbench in SystemC.

The code in Figure 3 starts with an include directive. The include directive refers to a header file called d_ff_tb.h. The header file defines a class called d_ff_tb, as

class d_ff_tb : sc_core::sc_module
{
  public: 
    d_ff_tb(sc_core::sc_module_name name); 
    d_ff d_ff_0; 
  private:
    sc_clock clk; 
    sc_signal<bool> d_ff_data_in; 
    sc_signal<bool> d_ff_data_out;
    void stim_gen();
    void reporter(); 
}; 

The code in Figure 3 defines the functions stim_gen and reporter to be SystemC processes. This is done using the keywords SC_THREAD and SC_METHOD.

The process named reporter is responsible for printout of results, and it is made sensitive to changes in the clock signal, or changes in the input signal to the D flip-flop, as

    sensitive << d_ff_0.clk.pos();
    sensitive << d_ff_data_in; 

The clock signal is defined by a variable called clk. The actual shape of the clock signal is defined by the arguments to the constructor for the class clk, as seen in the line

    clk("d_ff_clk", 4, SC_NS, 1.0)

The input signal to the D flip-flop is defined by the variable d_ff_data_in. The values used for the input signal are defined in the function stim_gen, as

void d_ff_tb::stim_gen()
{
    d_ff_data_in.write(true);
    wait(1, SC_NS);
    d_ff_data_in.write(false);
    wait(5, SC_NS);
    d_ff_data_in.write(true);
    wait(3, SC_NS);
    d_ff_data_in.write(false);
    wait(); 
}

Build and Run

This is the SystemC/TLM layer The other layers are: VHDL Verilog

The D flip-flop in Figure 2 and the testbench in Figure 3 can be compiled using

g++ -c -I /usr/local/systemc-2.3.1a/include d_ff_tb.cpp
g++ -c -I /usr/local/systemc-2.3.1a/include d_ff.cpp
g++ -c -I /usr/local/systemc-2.3.1a/include d_ff_tb_main.cpp

The combined system, containing the D flip-flip and the testbench, can be created by linking the object files from the compilation into an executable program. The linking is simplified by setting an environment variable L_SYSTEMC, as described in Section Make it Run.

An executable program can be generated by giving the command

g++ -o d_ff_tb_main d_ff_tb_main.o d_ff_tb.o d_ff.o -L $L_SYSTEMC -lsystemc

The program can now be run, in Linux by giving the command

LD_LIBRARY_PATH=$L_SYSTEMC ./d_ff_tb_main

and on Mac by giving the command

./d_ff_tb_main 

The resulting printout is shown in Figure 4.

        SystemC 2.3.1-Accellera --- Jan  3 2017 19:23:14
        Copyright (c) 1996-2014 by all Contributors,
        ALL RIGHTS RESERVED
Time: 0 s, data_in=0, data_out=0
Time: 0 s, data_in=1, data_out=0

Info: (I702) default timescale unit used for tracing: 1 ps \
(d_ff_tb_wave.vcd)
Time: 1 ns, data_in=0, data_out=1
Time: 4 ns, data_in=0, data_out=1
Time: 6 ns, data_in=1, data_out=0
Time: 8 ns, data_in=1, data_out=0
Time: 9 ns, data_in=0, data_out=1
Time: 12 ns, data_in=0, data_out=1
Time: 16 ns, data_in=0, data_out=0

Figure 4. Printout from running the testbench in Figure 3.

The printout in Figure 4 shows the values of data_in and data_out for a sequence of time instants. The time instants are defined by the sensitivity statements for the SystemC method named reporter in Figure 3, with the effect that the SystemC method reporter is executed whenever the clock signal has a rising edge, or the variable d_ff_data_in changes value. The changes for the variable d_ff_data_in are defined in the function d_ff_tb::stim_gen in Figure 3.

The printout in Figure 4 also contains a printout of the file name d_ff_tb_wave.vcd. This is a file where waveform data are stored. The display of waveforms is treated in Section Making Waves.

Making Waves

This is the SystemC/TLM layer The other layers are: VHDL Verilog

The testbench in Figure 3 generates printouts as shown in Figure 4. The printouts show values of digital signals, each having the value one or zero. We can represent these signals as waveforms, with the level of the waveform being one or zero. Thinking of the value one as a high voltage level, and the value zero as a low voltage level, we can think of the waveforms as representing actual voltages, in an actual digital system.

A waveform can be visualized using the GTKWave program. We can download a GTKWave version for Mac, in the form of a zip-file that contains an executable GTKWave program. The GTKWave program can be started from a Mac Terminal, by giving the command open followed by the app file name of the program. As an example, I could start the program by doing

open /Users/oladahl/prog/gtkwave/gtkwave.app

A GTKWave version for Ubuntu can be installed in Ubuntu, by giving the command

sudo apt-get install gtkwave

The program can then be started by giving the command gtkwave.

A waveform can be generated from SystemC by calling the function sc_create_vcd_trace_file, and then calling a function sc_trace, for determining which data that shall be recorded.

For the D flip-flop example, with build and run instructions as described in Section Build and Run, we put the waveform-related code in the file d_ff_tb_main.cpp. This file is referred to in the compilation commands, shown in Section Build and Run, and its contents are shown here, as

#include "systemc.h"
#include "d_ff_tb.h"

int sc_main(int argc, char* argv[])
{
    d_ff_tb d_ff_tb_0("d_ff_tb_0");
    
    sc_trace_file *d_ff_tb_wave =
    sc_create_vcd_trace_file("d_ff_tb_wave");

    sc_trace(d_ff_tb_wave, d_ff_tb_0.d_ff_0.clk, "clk");
    sc_trace(d_ff_tb_wave, d_ff_tb_0.d_ff_0.data_in, "data_in");
    sc_trace(d_ff_tb_wave, d_ff_tb_0.d_ff_0.data_out,
         "data_out");
    
    sc_start(17, SC_NS); 

    return 0;
}

Waveforms, generated from the testbench in Figure 3, are shown in Figure 5.

fig_d_ff_tb_wave_systemc_tlm
Figure 5. Waveforms, obtained from running the testbench in Figure 3.

We see in Figure 5 how the waveforms correspond to the printouts shown in Figure 4.

Storing Data in Registers

When a computer executes instructions, it often needs intermediate storage places. Reading instructions from memory, writing results back to memory. For example adding numbers, and writing back only when all numbers have been added. Then registers can be used, to hold the intermediate sum, while the calculation is ongoing. We can refer to such a row using the term register. Another use of registers is for addressing. In this scenario, the value stored in the register is an address, addressing a part of the memory. One such register is holding an address pointing to the next instruction to be executed. This register is referred to as the program counter.

A Register

A D flip-flop can store one bit. We can imagine a register as a row of D flip-flops, each storing one bit, with the possibility to load new values into all D flip-flops simultaneously.

This is the SystemC/TLM layer The other layers are: VHDL Verilog

A D flip-flop can store one bit. We can imagine a register as a row of D flip-flops, each storing one bit, with the possibility to load new values into all D flip-flops simultaneously.

A register implementation in SystemC is shown in Figure 6.

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#include "n_bit_register.h"

SC_HAS_PROCESS(n_bit_register);

n_bit_register::n_bit_register(sc_core::sc_module_name name, int N):
    sc_module(name)
{
    reg_value_max = (1 << N) - 1;
    cout << "reg max is " << reg_value_max << "\n"; 
    SC_METHOD(update);
    sensitive << clk.pos(); 
}

void n_bit_register::update()
{
    reg_value = data_in.read();
    data_out.write(reg_value);
    // std::cout << "data_in " << data_in.read() << "\n"; 
    // std::cout << "reg_value " << reg_value << "\n"; 
    // std::cout << data_out << "\n"; 
}

n_bit_register.cpp

Figure 6. A register in SystemC.

The code in Figure 6 starts with an include directive. The include directive refers to header file defines a class called n_bit_register, as

class n_bit_register : sc_core::sc_module
{
  public: 
    sc_in<bool> clk;
    sc_in<int> data_in;
    sc_out<int> data_out;
    n_bit_register(sc_core::sc_module_name name, int N); 
  private:
    void update();
    int reg_value;
    int reg_value_max;
}; 

The class defines two inputs, called clk and data_in, and one output, called data_out.

The class also defines a function called update, and a variable called reg_value.

The variable reg_value will contain the actual value stored in the register.

The code in Figure 6 defines the function update to be a SystemC processes. In addition, it defines the module n_bit_register to be sensitive to rising edges of the clock signal. The result of the sensitivity definition is that the function update will be called at every positive edge of the clock signal.

We see, from the contents of the function update, that it ensures that the state variable reg_value is updated at every rising edge of the clock.

An assignment of the variable data_out also done, inside the function update. This assignment ensures that the output data_out has the same value as the current value of the state variable reg_value.

A Testbench

An external module, referred to as a testbench, can be used for the purpose of generating input signals to, and observing output signals from, the register in Figure 6.

In the testbench module, we use a parameter, to specify the width of the register.

This is the SystemC/TLM layer The other layers are: VHDL Verilog

The parameter is defined using a C++ define directive, as

#define N 4

The clock signal is generated using a variable of the class sc_clock, defined as

    sc_clock clk; 

The actual clock generation is done using parameters specified in the instantiation of the clk variable. This is done in by instantiating the clk variable inside the constructor. The constructor is implemented as

n_bit_register_tb::n_bit_register_tb(sc_core::sc_module_name name):
    sc_module(name),
    n_bit_register_0("n_bit_register_0", N),
    clk("n_bit_register_clk", 4, SC_NS, 1.0), 
    data_in_value(1)
{
    n_bit_register_0.clk(clk); 
    n_bit_register_0.data_in(n_bit_register_data_in); 
    n_bit_register_0.data_out(n_bit_register_data_out);
    SC_METHOD(stim_gen);
    sensitive << n_bit_register_0.clk.pos();
    SC_METHOD(reporter);
    sensitive << n_bit_register_0.clk.pos();
}

and the instantiation of the clk variable is done in the constructor initialization block, as

    clk("n_bit_register_clk", 4, SC_NS, 1.0), 

The generation of input signals to the register in Figure 6 is done using a SystemC process, defined as a function as

void n_bit_register_tb::stim_gen()
{
    n_bit_register_data_in.write(data_in_value++);
}

and made into a process by the SC_METHOD directive. The SC_METHOD directive is used in the constructor, as shown above.

The input signal and the output signal are defined as

    sc_signal<int> n_bit_register_data_in; 
    sc_signal<int> n_bit_register_data_out;

The signals are used in the instantiation of the register, which is done in the constructor, shown above.

The reporting of the results is done in a process, defined as a function as

void n_bit_register_tb::reporter()
{
    std::cout << "Time: " << sc_time_stamp(); 
    std::cout << ", data_in=" << std::bitset<N> (n_bit_register_data_in.read());
    std::cout << ", data_out=" << std::bitset<N> (n_bit_register_data_out.read())
          << std::endl;
}

and made into a process by the SC_METHOD directive. The SC_METHOD directive is used in the constructor, as shown above.

Build and Run

The register in Figure 6 and a testbench, with code as shown in in Section A Testbench, can be built and run.

A makefile can be created. The makefile can contain commands for building and running the register and the testbench.

This is the SystemC/TLM layer The other layers are: VHDL Verilog

A makefile is shown in Figure 7.

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UNITS := n_bit_register n_bit_register_tb
HEADER_ONLY_UNITS := 
MAIN_UNIT := n_bit_register_tb_main

OBJS := $(addsuffix .o, $(UNITS) $(MAIN_UNIT))
HEADERS := $(addsuffix .h, $(UNITS) $(HEADER_ONLY_UNITS))

SYSTEMC := /usr/local/systemc-2.3.1a
INCLUDE_DIR := $(SYSTEMC)/include
UNAME := $(shell uname)
ifeq ($(UNAME),Darwin)
  LIB_DIR_NAME := lib-macosx64
else
  LIB_DIR_NAME := lib-linux64
endif
LIB_DIR := $(SYSTEMC)/$(LIB_DIR_NAME)/
LIB_NAME := systemc

$(MAIN_UNIT): $(OBJS)
    g++ -o $@ $^ -L $(LIB_DIR) -l $(LIB_NAME)

%.o: %.cpp $(HEADERS)
    g++ -c -Wall -g -I $(INCLUDE_DIR) $<

.PHONY: clean

clean: 
    rm $(MAIN_UNIT) $(OBJS)

Makefile

Figure 7. A makefile for building and running the register in Figure 6.

It can be seen, in the makefile in Figure 7, that the g++ command is used, in the same way as described in Section Build and Run in Chapter Storing one bit.

Assume the register is stored in files named n_bit_register.h and n_bit_register.cpp, and the testbench is stored in files named n_bit_register_tb.h and n_bit_register_tb.cpp. Assume also that a main program is stored in a file named n_bit_register_tb_main.cpp.

Running the makefile, by giving the command make results in printouts, as

$ make
g++ -c -Wall -g -I /usr/local/systemc-2.3.1/include n_bit_register.cpp
g++ -c -Wall -g -I /usr/local/systemc-2.3.1/include n_bit_register_tb.cpp
g++ -c -Wall -g -I /usr/local/systemc-2.3.1/include n_bit_register_tb_main.cpp
g++ -o n_bit_register_tb_main n_bit_register.o n_bit_register_tb.o n_bit_register_tb_main.o -L /usr/local/systemc-2.3.1/lib-macosx64/ -lsystemc 

A script file can be created, and used for running the simulated register and the testbench. Using a script file named run.sh, with contents as

#!/bin/bash

SYSTEMC=/usr/local/systemc-2.3.1a
LIB_DIR=$SYSTEMC/lib-linux64/

LD_LIBRARY_PATH=$LIB_DIR ./n_bit_register_tb_main

for running the simulation, gives the result as shown in Figure 8.

systemc_tlm:-$ ./run.sh 

        SystemC 2.3.1-Accellera --- Jan  3 2017 19:23:14
        Copyright (c) 1996-2014 by all Contributors,
        ALL RIGHTS RESERVED
reg max is 15
Time: 0 s, data_in=0000, data_out=0000
Time: 0 s, data_in=0001, data_out=0000

Info: (I702) default timescale unit used for tracing: 1 ps (n_bit_register_tb_wave_systemc_tlm.vcd)
Time: 4 ns, data_in=0010, data_out=0001
Time: 8 ns, data_in=0011, data_out=0010
Time: 12 ns, data_in=0100, data_out=0011
Time: 16 ns, data_in=0101, data_out=0100

Figure 8. Printouts from a simulation of the register in Figure 6.

We can generate waveforms, in the same way as described in Section Making Waves. The resulting waveform, for the register with printouts as shown above, is displayed in Figure 9.

fig_n_bit_register_tb_wave_systemc_tlm
Figure 9. Waveforms from a simulation with printouts as shown in Figure 8.

Our First Instruction

A computer executes programs by following instructions. The instructions belong to an an instruction set. As mentioned in Chapter Welcome, we will use a subset of the OR1K instruction set as the instruction set for our computer.

As a first step, we will try to build a computer with only one instruction. Although somewhat restricted, this computer will be able to

We will start with deciding on a program to run on our computer. The program will be stored in a memory, and its instructions will be read, one by one, and actions will be taken.

A Program

From the OpenRisc Architecture page we can find the OpenRISC 100 Architecture Manual.

From the OpenRISC 100 Architecture Manual, we find the instruction l.movhi rD, K on page 81.

We see that this instruction takes a 16-bit value K, and shifts it left by 16-bits, and then places the resulting value in the register rD.

We also see the instruction format for l.movhi rD, K, with its different fields. There are

We can write the instruction, with the fields as described above, as a 32-bit binary word. This gives

000110DDDDD----0KKKKKKKKKKKKKKKK

The binary instruction format for l.movhi rD, K can also be seen in Section 17 of the OpenRISC 100 Architecture Manual.

Suppose we want to make a program that starts with

  1. storing the value 1 in r0
  2. storing the value 2 in r1
  3. storing the value 3 in r3

The program should then store the value 0 in registers r0, r1, and r2.

This program can be implemented by using the instruction l.movhi rD, K, and choosing different values for rD and K.

Using the instruction format as described above, we find that the resulting program can be written as

00011000000----00000000000000001
00011000001----00000000000000010
00011000010----00000000000000011
00011000000----00000000000000000
00011000001----00000000000000000
00011000010----00000000000000000

Grouping the binary digits in groups of four gives

0001 1000 000- ---0 0000 0000 0000 0001
0001 1000 001- ---0 0000 0000 0000 0010
0001 1000 010- ---0 0000 0000 0000 0011
0001 1000 000- ---0 0000 0000 0000 0000
0001 1000 001- ---0 0000 0000 0000 0000
0001 1000 010- ---0 0000 0000 0000 0000

We can convert the program to a representation where we use hexadecimal numbers. This conversion results in the program shown in Figure 10.

18000001
18200002
18400003
18000000
18200000
18400000

Figure 10. A program using a l.movhi instruction for writing values into registers.

Addressing a Memory

We can store a program, like the program shown in Figure 10, in a memory.

The program in Figure 10 consists of instructions. Each instruction is represented by a 32-bit word.

As a first step towards executing the program, we can create a program counter that reads the 32-bit instructions, one by one, from the memory.

Reading an instruction is done by using the program counter value to address the memory. When we are done with reading an instruction, we might want to read the next instruction.

We could imagine a program counter that refers to a specific 32-bit word, stored in the memory. In a program with 32-bit instructions, like the program in Figure 10, this makes it possible to read the next instruction by incrementing the program counter with one.

Another alternative is to let the program counter represent an address expressed in bytes. In such a situation, we can read the next instruction by incrementing the program counter with four. This type of addressing is referred to as byte-addressing.

This is the SystemC/TLM layer The other layers are: VHDL Verilog

We can implement a memory in SystemC by using TLM (TBD URL). We use TLM as a means to model communication over a memory-mapped bus.

A memory implementation in Systemc_Tlm is shown in Figure 11.

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#ifndef MEMORY_H
#define MEMORY_H

#include "tlm.h"
#include "tlm_utils/simple_target_socket.h"

class Memory : sc_core::sc_module
{
public: 
    tlm_utils::simple_target_socket<Memory> socket; 
    Memory(sc_core::sc_module_name name, int size); 
private: 
    void read_contents_from_file(const char *file_name, int *mem, int max_values);
    void b_transport(tlm::tlm_generic_payload& trans, sc_core::sc_time& delay); 
    unsigned int size;
    int *mem;
}; 

#endif

memory.h

Figure 11. A memory in Systemc_Tlm.

We can implement a program counter SystemC by using TLM (TBD URL). We use TLM as a means to model communication over a memory-mapped bus.

Create a pc that reads addresses expressed in bytes. Meaning that it increments itself with four for each instruction read.

A program counter implementation in Systemc_Tlm is shown in Figure 12.

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#ifndef PC_H
#define PC_H

#include "tlm.h"
#include "tlm_utils/simple_initiator_socket.h"

class Pc : sc_core::sc_module
{
public: 
    tlm_utils::simple_initiator_socket<Pc> socket; 
    Pc(sc_core::sc_module_name name); 
private:
    void process(); 
    int pc_value; 
    int data_read; 
}; 

#endif

pc.h

Figure 12. A program counter in Systemc_Tlm.

Connect the pc and the memory into a design, so that when it runs, the program is read, and printed.

We define signals, such as pc

    tlm_utils::simple_initiator_socket<Pc> socket; 

and data read from the memory

    int data_read; 

and we do not have a clock signal.

Instead we have TBD.

Decoding the Instruction

Running the program

Hello Assembly World

The Program

l.andi r0, r0, 0
l.addi r0, r0, 0x9
l.slli r0, r0, 28

l.andi r1, r1, 0
l.addi r1, r1, 72
l.sw 0(r0), r1

Tools

Testing in QEMU

or1k-elf-as -o start.o start.s or1k-elf-ld -T default.ld -o prog.elf start.o /home/ola/prog/qemu/bin/qemu-system-or32 -nographic -kernel prog.elf

Extending our Computer

And with Immediate Half Word

We see the instruction format for l.andi rD, rA, K, with its different fields. There are

We can write the instruction, with the fields as described above, as a 32-bit binary word. This gives

101001DDDDDAAAAAKKKKKKKKKKKKKKKK

The binary instruction format for l.andi rD, rA, K can also be seen in Section 17 of the OpenRISC 100 Architecture Manual.

Suppose we want to make a program that uses the andi

In assembly code, this program would be

    l.movhi r0, 0
    l.ori r0, r0, 15
    l.andi r1, r0, 7
    l.andi r2, r1, 3
    l.andi r3, r2, 1

Using the instruction format as described above, we find that the corresponding machine code program becomes

000110 00000 00000 0000000000000000
101010 00000 00000 0000000000001111
101001 00001 00000 0000000000000111
101001 00010 00001 0000000000000011
101001 00011 00010 0000000000000001

Grouping the binary digits in groups of four gives

0001 1000 0000 0000 0000 0000 0000 0000
1010 1000 0000 0000 0000 0000 0000 1111
1010 0100 0010 0000 0000 0000 0000 0111
1010 0100 0100 0001 0000 0000 0000 0011
1010 0100 0110 0010 0000 0000 0000 0001

We can convert the program to a representation where we use hexadecimal numbers. This conversion results in the program shown in Figure 13.

18000000
A800000F
A4200007
A4410003
A4620001

Figure 13. A program using the instruction l.andi.

Store to memory

Running the Program

Hello C World

The Program

Tools

Testing in QEMU

Extending our Computer

Running the Program