Hello world

A simple example will get us started. We use a classical "Hello, world'' example, which will do nothing meaningful except printing a text string. The code for the example is shown in Figure 1. The code for the example is from the GHDL guide. We will start using GHDL in Section Getting some tools.

use std.textio.all;

entity hello_world is
end hello_world;

architecture behavior of hello_world is
    variable the_line: line;
    write(the_line, String'("Hello, world"));
    writeline(output, the_line);
  end process;
end behavior;

Figure 1. A hello world example in VHDL.

This the VHDL view - other views are Verilog - SystemC-TLM

The code in Figure 1 starts with a use clause. The purpose of this clause is to indicate which VHDL libraries that will be used. In this case we use one library, with functionality for printing text.

The code in Figure 1 contains an entity. The entity is empty, since we do not have any input ports or output ports.

Then comes the architecture part, where a process is defined.

The process assigns a string to a variable called the_line. The string is then printed, and a call to wait is done, for the purpose of pausing the simulation.

We remark that the code in Figure 1 generates an artificial, simulated behavior. It does not provide any code that can be used for synthesizing actual hardware.

You can read about VHDL in Wikipedia, and at other places. A book called Free Range VHDL is available for free download. You may also want to look at this VHDL Guide from Doulos.