Build and run

The D flip-flop in Figure 2 and the testbench in Figure 3 can be analyzed using

ghdl -a d_ff.vhdl 
ghdl -a d_ff_tb.vhdl 

The combined system, containing the D flip-flip and the testbench, can be elaborated by the command

ghdl -e d_ff_tb

The simulation can be run by giving the command

ghdl -r d_ff_tb

The resulting printout is shown in Figure 4.

d_ff_tb.vhdl:63:8:@1ns:(report note): data_in='0', data_out='U'
d_ff_tb.vhdl:63:8:@4ns:(report note): data_in='0', data_out='U'
d_ff_tb.vhdl:63:8:@6ns:(report note): data_in='1', data_out='0'
d_ff_tb.vhdl:63:8:@8ns:(report note): data_in='1', data_out='0'
d_ff_tb.vhdl:63:8:@9ns:(report note): data_in='0', data_out='1'
d_ff_tb.vhdl:63:8:@12ns:(report note): data_in='0', data_out='1'

Figure 4. Printout from running the testbench in Figure 3.

This the VHDL view - other views are Verilog - SystemC-TLM

The printout in Figure 4 shows the values of data_in and data_out for a sequence of time instants. The time instants are defined by an if-statement inside the reporter process in Figure 3, as

  reporter: process(clk, d_ff_data_in) is
  begin
    if (rising_edge(clk) or d_ff_data_in'event) then
       report "data_in=" & std_logic'image(d_ff_data_in) & 
              ", data_out=" & std_logic'image(d_ff_data_out);
    end if; 
  end process; 

with the effect that a printout is done whenever the clock signal has a rising edge, or the variable d_ff_data_in changes value. The changes for the variable d_ff_data_in are defined in the stim_gen process in Figure 3.