Build and run

A system, containing the D flip-flop in Figure 2 and the testbench in Figure 3, can be analyzed and built using the command

iverilog -o d_ff_tb d_ff.v d_ff_tb.v

The simulation can be run by giving the command

vvp d_ff_tb

The resulting printout is shown in Figure 4.

VCD info: dumpfile d_ff_tb_wave.vcd opened for output.
At time                    0, data_in=1, data_out=1
At time                    1, data_in=0, data_out=1
At time                    4, data_in=0, data_out=0
At time                    6, data_in=1, data_out=0
At time                    8, data_in=1, data_out=1
At time                    9, data_in=0, data_out=1
At time                   12, data_in=0, data_out=0

Figure 4. Printout from running the testbench in Figure 3.

This the Verilog view - other views are VHDL - SystemC-TLM

The printout in Figure 4 shows the values of data_in and data_out for a sequence of time instants. The time instants are defined by a $monitor statement inside an initial block in Figure 3, as

   initial begin
      $monitor("At time %t, data_in=%b, data_out=%b", 
               $time, d_ff_data_in, d_ff_data_out);
      #16 $finish;

with the effect that a printout is done whenever the time changes, or one of the variables d_ff_data_in or d_ff_data_out changes value. The changes for the variable d_ff_data_in are defined in an initial block in Figure 3 as

   initial begin
      #1 d_ff_data_in = 0;
      #5 d_ff_data_in = 1;
      #3 d_ff_data_in = 0;

The printuout in Figure 4 also contains a printout of the file name d_ff_tb_wave.vcd. This is a file where waveform data are stored. The display of waveforms is treated in Section Making waves.