The D flip-flop implementation in Figure 2 has inputs and outputs. An external module, referred to as a testbench, can be used for the purpose of generating input signals to the D flip-flop, and observing output signals from the D-flip-flop.
A Verilog testbench is shown in Figure 3.
`timescale 1ns / 1ns module d_ff_tb; reg clk = 1; reg d_ff_data_in = 1; wire d_ff_data_out; initial begin $monitor("At time %t, data_in=%b, data_out=%b", $time, d_ff_data_in, d_ff_data_out); #16 $finish; end initial begin #1 d_ff_data_in = 0; #5 d_ff_data_in = 1; #3 d_ff_data_in = 0; end initial begin $dumpfile("d_ff_tb_wave.vcd"); $dumpvars(0,d_ff_0); end always #2 clk = !clk; d_ff d_ff_0(clk, d_ff_data_in, d_ff_data_out); endmodule
Figure 3. A D flip-flop testbench in Verilog.
The testbench in Figure 3 starts with a definition of the time scale, stating that nanoseconds (ns) will be used as the time unit. A register variable called clk is defined. This variable represents the clock signal. The actual shape of the clock signal is defined by the line
always #2 clk = !clk;
initial begin #1 d_ff_data_in = 0; #5 d_ff_data_in = 1; #3 d_ff_data_in = 0; end
The testbench in Figure 3 is a behavioral model. A behavioral model can be used in simulation, but can not be synthesized into a working digital system, for use in e.g. an FPGA or an ASIC.