A D flip-flop

The value of a bit can be stored in a building block called D flip-flop.

A D flip-flop stores one bit of data. A new value can be stored when a clock signal changes value. A component which can change its stored value only when a clock signal changes is called a synchronous component.

A D flip-flop implementation in Verilog is shown in Figure 2.

module d_ff(clk, data_in, data_out);

   input clk;
   input data_in;
   output data_out;

   wire clk, data_in;

   reg 	reg_value;

   always @(posedge clk)
     reg_value <= data_in;
    
   assign data_out = reg_value;

endmodule    

Figure 2. A D flip-flop in Verilog.

This the Verilog view - other views are VHDL - SystemC-TLM

The code in Figure 2 defines a module. The module has two inputs, called clk and data_in, and one output, called data_out.

The input variables clk and data_in are defined using the keyword input and the output variable data_out is defined using the keyword output.

The input variables clk and data_in are also defined using the keyword wire.

The module defines a register variable called reg_value. The variable reg_value is defined using the keyword reg.

The variable reg_value will contain the actual value stored in the D flip-flop.

The variable reg_value is called a state variable.

An always block is defined using the keyword always. Following the keyword always is an indication, using the word posedge, stating that the actions in the always block shall take place at every rising edge of the clock signal. We see that the only action taken is to assign the value of the input data_in to the state variable reg_value. This assignment ensures that the state variable reg_value is updated at every rising edge of the clock.

An assignment of the variable data_out is done, outside of the always block. This assignment ensures that the output data_out has the same value as the current value of the state variable reg_value.