A D flip-flop

The value of a bit can be stored in a building block called D flip-flop.

A D flip-flop stores one bit of data. A new value can be stored when a clock signal changes value. A component which can change its stored value only when a clock signal changes is called a synchronous component.

A D flip-flop implementation in SystemC is shown in Figure 2.

#include "d_ff.h"

SC_HAS_PROCESS(d_ff);

d_ff::d_ff(sc_core::sc_module_name name):
    sc_module(name) 
{
    SC_METHOD(update);
    sensitive << clk.pos(); 
}

void d_ff::update()
{
    reg_value = data_in.read();
    data_out.write(reg_value);
}

Figure 2. A D flip-flop in SystemC.

This the SystemC-TLM view - other views are VHDL - Verilog

The code in Figure 2 starts with an include directive. The include directive refers to a header file called d_ff.h. The header file defines a class called d_ff, as

class d_ff : sc_core::sc_module
{
  public: 
    sc_in<bool> clk;
    sc_in<bool> data_in;
    sc_out<bool> data_out;
    d_ff(sc_core::sc_module_name name); 
  private:
    void update();
    bool reg_value;
}; 

The class defines two inputs, called clk and data_in, and one output, called data_out.

The class also defines a function called update, and a variable called reg_value. The variable reg_value is defined using the keyword bool.

The variable reg_value will contain the actual value stored in the D flip-flop.

The variable reg_value is called a state variable.

The class inherits from another class, called sc_core::sc_module. In this way, the class becomes a SystemC module.

The code in Figure 2 defines the function update to be a SystemC process. This is done using the keyword SC_METHOD. In addition, it defines the module d_ff to be sensitive to rising edges of the clock signal. The result of the sensitivity definition is that the function update will be called at every positive edge of the clock signal.

We see, from the contents of the function update, that the only action taken is to assign the value of the input data_in to the state variable reg_value. This assignment ensures that the state variable reg_value is updated at every rising edge of the clock.

An assignment of the variable data_out also done, inside the function update. This assignment ensures that the output data_out has the same value as the current value of the state variable reg_value.