Build and Run

The register in Figure 6 and a testbench, with code as shown in in Section A testbench, can be built and run.

A makefile can be created. The makefile can contain commands for building and running the register and the testbench. A makefile is shown in Figure 7.

SOURCES := n_bit_register.v n_bit_register_tb.v

n_bit_register_tb: $(SOURCES)
	iverilog -o $@ $^

.PHONY: clean

clean: 
	rm n_bit_register_tb

Figure 7. A makefile for building and running the register in Figure 6.

This the Verilog view - other views are VHDL - SystemC-TLM

It can be seen, in the makefile in Figure 7, that the iverilog command is used, in the same way as described in Section Build and run in Chapter Storing one bit.

Assume the register is stored in a file named n_bit_register.v, and the testbench is stored in a file named n_bit_register_tb.v. Running the makefile, by giving the command make results in printouts, as

$ make
iverilog -o n_bit_register_tb n_bit_register.v n_bit_register_tb.v

A script file can be created, and used for running the simulated register and the testbench. Using a script file named run.sh, with contents as

#!/bin/bash

vvp n_bit_register_tb

for running the simulation, gives the result as shown in Figure 8.

$ ./run.sh 
VCD info: dumpfile n_bit_register_tb_wave_verilog.vcd opened for output.
At time                    0, data_in=0001, data_out=0001
At time                    4, data_in=0010, data_out=0001
At time                    8, data_in=0011, data_out=0010
At time                   12, data_in=0100, data_out=0011
At time                   16, data_in=0101, data_out=0100

Figure 8. Printouts from a simulation of the register in Figure TBD.

This the Verilog view - other views are VHDL - SystemC-TLM

We can generate waveforms, in the same way as described in Section TBD. The resulting waveform, for the register with printouts as shown above, is displayed in Figure 9.

Figure 9. Waveforms from a simulation with printouts as shown in Figure TBD.