Build and Run

The register in Figure 6 and a testbench, with code as shown in in Section A testbench, can be built and run.

A makefile can be created. The makefile can contain commands for building and running the register and the testbench. A makefile is shown in Figure 7.

UNITS := n_bit_register n_bit_register_tb
MAIN_UNIT := n_bit_register_tb_main

OBJS := $(addsuffix .o, $(UNITS) $(MAIN_UNIT))
HEADERS := $(addsuffix .h, $(UNITS) $(HEADER_ONLY_UNITS))

SYSTEMC := /usr/local/systemc-2.3.1a
UNAME := $(shell uname)
ifeq ($(UNAME),Darwin)
  LIB_DIR_NAME := lib-macosx64
  LIB_DIR_NAME := lib-linux64
LIB_NAME := systemc

	g++ -o $@ $^ -L $(LIB_DIR) -l $(LIB_NAME)

%.o: %.cpp $(HEADERS)
	g++ -c -Wall -g -I $(INCLUDE_DIR) $<

.PHONY: clean

	rm $(MAIN_UNIT) $(OBJS)

Figure 7. A makefile for building and running the register in Figure 6.

This the SystemC-TLM view - other views are VHDL - Verilog

It can be seen, in the makefile in Figure 7, that the g++ command is used, in the same way as described in Section Build and run in Chapter Storing one bit.

Assume the register is stored in files named n_bit_register.h and n_bit_register.cpp, and the testbench is stored in files named n_bit_register_tb.h and n_bit_register_tb.cpp. Assume also that a main program is stored in a file named n_bit_register_tb_main.cpp.

Running the makefile, by giving the command make results in printouts, as

$ make
g++ -c -Wall -g -I /usr/local/systemc-2.3.1/include n_bit_register.cpp
g++ -c -Wall -g -I /usr/local/systemc-2.3.1/include n_bit_register_tb.cpp
g++ -c -Wall -g -I /usr/local/systemc-2.3.1/include n_bit_register_tb_main.cpp
g++ -o n_bit_register_tb_main n_bit_register.o n_bit_register_tb.o n_bit_register_tb_main.o -L /usr/local/systemc-2.3.1/lib-macosx64/ -l systemc

A script file can be created, and used for running the simulated register and the testbench. Using a script file named, with contents as



LD_LIBRARY_PATH=$LIB_DIR ./n_bit_register_tb_main

for running the simulation, gives the result as shown in Figure 8.

systemc_tlm:-$ ./ 

        SystemC 2.3.1-Accellera --- Jan  3 2017 19:23:14
        Copyright (c) 1996-2014 by all Contributors,
reg max is 15
Time: 0 s, data_in=0000, data_out=0000
Time: 0 s, data_in=0001, data_out=0000

Info: (I702) default timescale unit used for tracing: 1 ps (n_bit_register_tb_wave_systemc_tlm.vcd)
Time: 4 ns, data_in=0010, data_out=0001
Time: 8 ns, data_in=0011, data_out=0010
Time: 12 ns, data_in=0100, data_out=0011
Time: 16 ns, data_in=0101, data_out=0100

Figure 8. Printouts from a simulation of the register in Figure TBD.

This the SystemC-TLM view - other views are VHDL - Verilog

We can generate waveforms, in the same way as described in Section Making waves. The resulting waveform, for the register with printouts as shown above, is displayed in Figure 9.

Figure 9. Waveforms from a simulation with printouts as shown in Figure 6.