A testbench

An external module, referred to as a testbench, can be used for the purpose of generating input signals to, and observing output signals from, the register in Figure 6.

In the testbench module, we use a parameter, to specify the width of the register. The parameter is defined as a Verilog parameter, as

   parameter N=4;

The clock signal is generated using a register variable named clk, defined as

   reg clk = 1;

The actual clock generation is done in an always block, as

   always #2 
     clk = !clk;

The generation of input signals to the register in Figure 6 is done using a Verilog process, as

   always @(posedge clk)
     reg_data_in <= reg_data_in + 1;

The input signal and the output signal are defined as

   reg [N-1:0] reg_data_in = 1'b1;
   wire[N-1:0] reg_data_out;

The signals are used in the instantiation of the register, which is done as

   n_bit_register #(.N(N)) reg_0(clk, reg_data_in, reg_data_out);

The reporting of the results is done in a process, as

   initial begin
      $monitor("At time %t, data_in=%b, data_out=%b", 
               $time, reg_data_in, reg_data_out);
      #16 $finish;
   end