A D flip-flop can store one bit. We can imagine a register as a row of D flip-flops, each storing one bit, with the possibility to load new values into all D flip-flops simultaneously.
A register implementation in Verilog is shown in Figure 6.
module n_bit_register(clk, data_in, data_out); parameter N = 8; input clk; input[N-1:0] data_in; output[N-1:0] data_out; wire clk; wire [N-1:0] data_in; reg [N-1:0] reg_value; always @(posedge clk) reg_value <= data_in; assign data_out = reg_value; endmodule
Figure 6. A register in Verilog.
The code in Figure 6 defines a module. The module has two inputs, called clk and data_in, and one output, called data_out.
An assignment of the variable data_out is done, outside of the always block. This assignment ensures that the output data_out has the same value as the current value of the state variable reg_value.